Memory cells in a DRAM device include a transistor and a capacitor to store a bit of data. The memory cells are ‘dynamic’ because their data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate of the device. To keep the data in the cells valid, each memory cell is periodically refreshed. Data in DRAM memory cells are refreshed every time the data is read out of the cell array into the sense amplifiers and subsequently rewritten into the cell.
DRAM devices consistent with the double data rate specification 3 (DDR3, as defined by JEDEC JESD79-3) have internal charge pumps that pump up the voltage from 1.5V (Vdd) to the voltage requirements required for word line boosts. The word line boost voltage is used during activation of a DRAM row (i.e., for opening a DRAM page). This internal voltage level varies across DRAM devices, but is generally in the range of 2.5-3.3V for a DDR3 device. The charge pumps included in these DRAM devices are 5-10% efficient and take up a significant die size area.
Proposed DDR4 specifications would instead allow DRAM devices to receive an external Voltage (Vpp) for DRAM internal word-line boosts. Vpp for these devices may be, for example, 3.3V as this value is readily available from the platform. These DRAM devices may internally regulate received power from 3.3V to the desired internal voltage level (e.g., ˜2.5V), or a memory module including these devices may include a voltage regulator (VR) to regulate the received power. Thus, it is understood that the elimination of charge pumps provides device power and die size savings.
DDR4 devices may receive Vpp via a DIMM connector. The worst case scenario for Vpp power is when all ranks on a DIMM and, as illustrated in FIG. 1 (discussed in further detail below), all banks included in the DRAM devices of said ranks are refreshed simultaneously. Power provided to said devices must account for this scenario.
The current requirement for Ipp may be, for example, ˜30 mA/device (for 2 Gbit DRAM devices including 16 banks). If, for example, there are 8 ranks with 18 devices each, then the max current requirement is 8×18×30=4.32 A. The DIMM connector would require 6 separate pins to receive this power, assuming each pin has a 0.75 A current carrying capability (i.e., 4.32 A/0.75 A per pin=6 pins). This current requirement may also require a new VR on some platforms as the current capability of existing 3.3V VRs may not be sufficient to receive 4.32 A current.
Thus, DRAM devices are needed that do not have as high of a current requirement to execute a self-refresh mode.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as a discussion of other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.